~inc:menu.inc~
Out UART1(debug port): 'Hello!'
~sys_ram0x60000f00=0x48~ ~sys_ram0x60000f00=0x65~ ~sys_ram0x60000f00=0x6c~ ~sys_ram0x60000f00=0x6c~ ~sys_ram0x60000f00=0x6f~ ~sys_ram0x60000f00=0x21~ ~sys_ram0x60000f00=0x0d~ ~sys_ram0x60000f00=0x0a~
Out UART0 tx: 'Hello!'
~sys_ram0x60000000=0x48~ ~sys_ram0x60000000=0x65~ ~sys_ram0x60000000=0x6c~ ~sys_ram0x60000000=0x6c~ ~sys_ram0x60000000=0x6f~ ~sys_ram0x60000000=0x21~ ~sys_ram0x60000000=0x0d~ ~sys_ram0x60000000=0x0a~ Read UART0 rx:~sys_ram0x60000000~

Variant 2
~start=0x60000000~ Read UART0 regs:
~start~=~xml_ram~
~start~=~xml_ram~
~start~=~xml_ram~
~start~=~xml_ram~

~start=0x40200000~ Read RAM:
~start~=~xml_ram~
~start~=~xml_ram~
~start~=~xml_ram~
~start~=~xml_ram~

Variant 2
RAM0x40200000=~sys_ram0x40200000~
~inc:footer.inc~